Author Topic: Gate all around Si Nanowire  (Read 2169 times)

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Offline Hassan

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Gate all around Si Nanowire
« on: January 27, 2014, 20:10 »
Hi,

I'd like help creating a Silicon (100) nanowire with SiO2 surrounding it on all sides. I'm not quite sure how to go about doing that. I am using ATK 13.8.

What I attempted:

Use the Wulff Constructor with (100 = 0.1 eV, the others 1 eV) to make the initial nanowire.
Then I try to use the Interface tool to attach SiO2 (Quartz from the database) to the nanowire. The problem is it doesn't look correct and the distances are too great. Plus I want to relax the entire structure afterwards to get a realistic nanowire/dielectric interface.

Any help with the proper procedure for doing this would be appreciated. Thanks.

Offline Anders Blom

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Re: Gate all around Si Nanowire
« Reply #1 on: January 27, 2014, 23:43 »
The interface tool will not work for this - it's for creating a flat interface. I would first use the Nanowire tool (not Wulff, although they are related, sort of) for Si. Then I would make a similar nanowire of SiO2, but after it's created I would cut out the middle to fit the Si part, and merge the configurations by simply dropping the Si nanowire stash item onto the SiO2 when it's active in the Builder.

Not entirely trivial - and probably not very realistic, since the Si-O bonds at the surface will be rather arbitrary.

A simpler choice, to begin with at least, would be to just represent the SiO2 with a dielectric region. Then at least the effects of the dielectric on the confinement of the wavefunction (compared to vacuum) could be included.

If a real model of SiO2 on Si is desired, one may need to perform some simulated growth, using MD. That need not be too difficult since there are fairly good Tersoff potentials for Si-SiO2, and which are included in ATK. Or, one can build a crude model and run an MD simulation on it to let it relax.

Offline Hassan

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Re: Gate all around Si Nanowire
« Reply #2 on: January 28, 2014, 18:09 »
I actually want to test out other dielectric interfaces, and I am running the Si-SiO2 interface simulation first because I know it's fairly standard and there is a lot of data out there about it. I want to sanity check my process first essentially, so doing a 'simulated' dielectric medium is out of the question.

As per your second suggestion, I tried doing MD simulation of the interface and I can't seem to get the settings right in terms of the ensemble etc. Every time I simulate I get bond lengths between the two interfaces to be huge and I can't get them to settle to a low energy configuration.

Let's say I was to just simulate an Si-SiO2 interface - without the GAA structure, how should I go about doing that in either MD or DFT sim? I tried doing OptimizeGeometry for DFT after using the interface tool for bulk Si-SiO2 and the interface I get looks really bad. I have attached the results of my sims.


Offline Anders Blom

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Re: Gate all around Si Nanowire
« Reply #3 on: January 28, 2014, 22:56 »
You probably need to stabilize the structure by keeping at least a layer of atoms fixed. Don't be afraid to make the structure a bit larger, even with 1000-4000 atoms the MD simulation with the classical potential will be very fast.

If you need more assistance I'll look into it tomorrow, let me know.