QuantumATK Forum
QuantumATK => Scripts, Tutorials and Applications => Topic started by: ANAS on October 8, 2012, 05:56
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hello ,
pls help me to plot drain induced barrier lowering vs channel length...... i want to plot for a single layer transistor (GNR) with channel length varies from 5 nm to 30 nm......
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It is quite obvious. You should perform the calculations for the GNR with different lengths in the range from 5nm to 30nm.
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for each gate length u draw Id-Vg (log scale) curves for Low Vds and high Vds, and then get a particular value of DIBL, collect a set of DIBL values for each gate length and plot.... simple ;D