QuantumATK Forum
QuantumATK => General Questions and Answers => Topic started by: h_almasi on March 8, 2015, 15:55
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Dear sir,
Could you please help me with simulating Vertical nanotransistors, structures like the one used in this paper
Graphene-based lateral heterostructure
transistors exhibit better intrinsic
performance than graphene-based
vertical transistors as post-CMOS devices [ DOI: 10.1038/srep06607],
I mean, how can I build such layered structures with the Builder and what setting I must use in the New Calculator ?
Thank you so much for your consideration. :)