QuantumATK Forum

QuantumATK => General Questions and Answers => Topic started by: Adila on June 3, 2015, 10:29

Title: Bias Voltage
Post by: Adila on June 3, 2015, 10:29

Dear all,

I am trying to run the IV characteristics of GNR FET. However, I am confused about the bias voltage. In most cases, bias voltage is supposed to be the drain voltage right? Therefore, thus this means that the IV Plot refers to Id versus Vd graph?

Thanks in advance.

Title: Re: Bias Voltage
Post by: Anders Blom on June 3, 2015, 13:07

"Bias" by itself doesn't mean much. But it also depends on what you simulate, so we use this term in a generic way. If you apply a voltage to the two electrodes, the difference is a bias. If your system is constructed such that the two electrodes correspond to source and drain, then  the bias is Vdd. If it's like a nanowire, you can add a gate, and apply a bias to this gate, which then is Vg and you can look at the transconductance, subthreshold swing, etc.

However, you can also simulate a gate stack as a twoprobe device, and then the bias is really Vg and the I-V curve would be for the leakage current.