QuantumATK Forum

QuantumATK => Scripts, Tutorials and Applications => Topic started by: ANAS on October 8, 2012, 05:56

Title: DIBL
Post by: ANAS on October 8, 2012, 05:56

hello ,
pls help me to plot drain induced barrier lowering vs channel length...... i want to plot for a single layer transistor (GNR) with channel length varies from 5 nm to 30 nm......

Title: Re: DIBL
Post by: zh on October 8, 2012, 08:51

It is quite obvious. You should perform the calculations for the GNR with different lengths in the range from 5nm to 30nm.

Title: Re: DIBL
Post by: ams_nanolab on November 15, 2012, 11:19

for each gate length u draw Id-Vg (log scale) curves for Low Vds and high Vds, and then get a particular value of DIBL, collect a set of DIBL values for each gate length and plot.... simple  ;D