Author Topic: Box on top of any S.C. surface  (Read 5971 times)

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Offline Dipankar Saha

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Box on top of any S.C. surface
« on: July 8, 2016, 13:44 »
Hello,
1)
When we include a spatial region on top of any S.C. surface... is there any requirement of maintaining a minimum separation/gap (between the box and the surface-atom) ?
2)
Is there any metric... which can be used for finding the  potential drop across the S.C. surface?

Regard_
Dipankar
« Last Edit: July 8, 2016, 13:47 by Dipankar Saha »

Offline Ulrik G. Vej-Hansen

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Re: Box on top of any S.C. surface
« Reply #1 on: July 8, 2016, 14:13 »
Could you please specify what you mean by "S.C. surface" ?

Offline Dipankar Saha

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Re: Box on top of any S.C. surface
« Reply #2 on: July 8, 2016, 14:20 »
S.C. -> Semiconductor.... / Say it's a 2D material e.g., MoS2...../ So at the surface, I have "S" atoms...


Offline Daniele Stradi

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Re: Box on top of any S.C. surface
« Reply #3 on: July 11, 2016, 09:55 »
Dear Dipahar,

1) No, in principle, there is no strict requirement about the gap. One important point, however, is that the spatial region should be thick enough to include at least 1 point of your real space grid. You will get an warning if this requirement is not complied.

2) To find the (electrostatic) potential drop, you have to calculate the HartreeDifferencePotential (or the ElectrostaticDifferencePotential, if you are using a version prior to ATK 2016) for the case V_bias==0 V and V_bias=/0. Then you have to subtract the two, and that will give you the potential drop across the semiconductor.

Offline Dipankar Saha

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Re: Box on top of any S.C. surface
« Reply #4 on: July 11, 2016, 12:31 »
Dear Daniele ,

1) I did not get .....what you tried to mean by saying ..."the spatial region should be thick enough to include at least 1 point of your real space grid" !!

2) I understand.... :)

Thanks & Regards _
Dipankar
« Last Edit: July 11, 2016, 12:53 by Dipankar Saha »

Offline Daniele Stradi

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Re: Box on top of any S.C. surface
« Reply #5 on: July 11, 2016, 13:06 »
Dear Dipankar,

the grid that you specify using the keyword "density_mesh_cutoff" (see https://www.quantumwise.com/documents/manuals/latest/ReferenceManual/index.html/ref.numericalaccuracyparameters.html) is a discrete 3D grid in real space. The potential is represented on this grid. A spatial region (for example, a metallic gate) modifies this potential in a certain region of space, but in order for this to work the spatial region MUST include the points of the grid.

Take a simple 1D example: let's say that we have a C vector of 10 Angstrom, and a grid of 1000 points along C. Hence, we will have a grid spacing of 100/1000 = 0.1 Angstrom, which means having a grid point every 0.1 Angstrom. If the thickness of the spatial region is, for example, 0.001 Angstrom, it can happen that NONE of the grid point is included in the spatial region. The minimum thickness, in this case, would be 0.1 Angstrom.

Daniele. 


Offline Dipankar Saha

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Re: Box on top of any S.C. surface
« Reply #6 on: July 11, 2016, 14:05 »
Dear Daniele ,

Thanks a lot for the details ...... :)
_______

Besides, I have attached one Fig. showing del_VH (along the transport direction), obtained for a Gated struct.  at Finite Vg (as well as, with a constant V_bias =0.1 V). Did you say that, if I subtract the zero-Vg result from this...., then I will get the surface potential plot?!!

Regards_
Dipankar
« Last Edit: July 11, 2016, 14:07 by Dipankar Saha »

Offline Daniele Stradi

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Re: Box on top of any S.C. surface
« Reply #7 on: July 13, 2016, 10:34 »
If you do finite V_G - V_G=0, you will obtain the difference between the two potentials. Then you can do a planar average to see the potential drop between the gate and the 2D layer.

Offline Dipankar Saha

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Re: Box on top of any S.C. surface
« Reply #8 on: July 13, 2016, 12:55 »
Then you can do a planar average to see the potential drop between the gate and the 2D layer.

Diff. in potetial is fine.../ Perhaps, the Planar Avg. of that... should also be taken along the transport direction (as, the del_VH curves are plotted along the c-axis)../ If so... then, what did you try to mean by saying_ "potential drop between the gate and the 2D layer" ?

Alternatively, if I take "a_average" of del_VH...the entire distribution is around the MoS2 thickness only!!!

Best_
Dipankar
« Last Edit: July 13, 2016, 12:57 by Dipankar Saha »

Offline Daniele Stradi

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Re: Box on top of any S.C. surface
« Reply #9 on: July 13, 2016, 13:03 »
Dear Dipankar,

it would be great if you can specify:
1) which configuration you are talking about (DeviceConfiguration, BulkConfiguration?)
2) which potential drop you are interested in (between the source and drain electrodes? between the gate and the device?)

Daniele

Offline Dipankar Saha

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Re: Box on top of any S.C. surface
« Reply #10 on: July 13, 2016, 14:09 »
Dear Daniele ,

Ohhh...okay..../ It's a device config. with a spatial region (dielectric+metal) for applying the gate bias.....  / I'm interested in finding the impact of the gate... on surface potential (though, the surface potential is plotted along the length of the channel, for any particular  drain-bias value...) !!

Thanks  & Regards_
Dipankar
« Last Edit: July 13, 2016, 19:13 by Dipankar Saha »