Thanks Anders,
Here is another question. I have attached three images of LDDOS for a GNR FET:
lddos_nogate_nocharge.png: Is for a GNR-device without any gate or bias. (This curve seems good)
lddos_pin.png: Is for a p-i-n structure with GNR no bias (charges are added to both electrodes) (We can see the slope in LDDOS as expected)
lddos_with_gate_volatge: Is the same structure with gate at -1V without any charges on electrode
Now in the third figure we see the conduction band moving up due to gate voltage. Why is the valence band not effected? Shouldn't it move up as well?
I in fact tried to have second gate with 0V but things didn't change.
Thanks in advance
-Arya