Author Topic: What is the effect of existence of a gate in NEGF device calculation?  (Read 330 times)

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Offline weixiang

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Dear experts,
Hi,
I have calculated the Projected local density of states (PLDOS) for a GNR device, with left/right electrodes&extensions p-doped and n-doped, respectively. The device and the corresponding PLDOS are shown as follows:


The PLDOS looks very reasonable since the left and right sides are p-doped and n-doped, the Fermi Level increase at the left side and decrease at the right side, while for the remaining undoped middle part, the Fermi level is at the middle. (Attached file test2.py)

Then I tried to include a gate in the middle without applying any gate voltage, and also calculated the PLDOS, their are shown as follows: (Attached file test3.py)



You can notice that just by introduce a gate in the middle, the Fermi level of the middle region increase to be the same as the left side. Why could this happen even when there is no gate voltage at all?
Initially I thought this could be some kind of Fermi level pinning effect, but I rejected this thought later since Fermi level pinning occurs where there is a surface state ( between semiconductor and Vacuum or between semiconductor and metal). But in my device there is no surface state in the middle.
I am stuck in interpreting this result and cannot understand what is the effect of the very existence of a gate region in my device. Can you help me explain it?

Any help will be appreciated!

Offline Daniele Stradi

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Dear Weixiang,

the gating effect that you see is correct, you are basically bending the electron bands on the right-hand side upward. You still see some pinning on the right-hand side because the right electrode is not gated.

If you try to simulate the undoped system, then you will see that that gating leads also to a symmetric electronic structure.

Best regards,
Daniele

Offline Petr Khomyakov

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In addition to the previous post, when you introduce a metal region in the near proximity to the ribbon, you change electrostatics of your system, since the metal gate screens out-of-plane electric fields,  modifying the charge distribution across your device, compared to the non-gate case, see Phys. Rev. B 82, 115437 (2010) to  get an idea of how that works for an infinitely-wide nanoribbon. 

Offline weixiang

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Thank you all for your kindly explanations!
I also did the calculations for PLDOS at finite gate voltages. Typically, I chose the gate voltage to be 0.5, 1.0, 1.5, 2.0, 2.5, and 3.0V and their result are shown as follows:

It is clear that they are very consistent of each other that with the gate voltage increases, the band shift downwards in the  middle region.
However, I am confused that why the 0.5V case (the first figure) is not consistent with the 0V case (the PLDOS without gate voltage) ? From the above image I get a sense that the lower the gate voltage the higher the position of mid-region-band, so the 0V case should have a higher mid-region-band than that of the 0.5V case. But the result shown otherwise. The 0V case is more or less like the 1V case, where their mid-region-band position are similar.
Can you give a explanation here?
Many thanks!

Offline Petr Khomyakov

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My guess is that the screening length in your device is pretty large, so you have to either try increasing the device central region or use higher doping level to achieve screening in the electrode extensions. In other words, you do not realize flat-band conditions in the electrode extensions for your current device setup/settings.

Offline weixiang

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Thanks! ;D

Offline weixiang

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Dear Petr,
Regarding your last reply to my question, I am just wondering if there is a way to quantitatively measure the screen length of my device?

You just mentioned that you do not realize flat-band conditions in the electrode extensions for your current device setup/settings
For clarity, by flat-band conditions, do you mean that both the conduction band and the valence band must be flat ( horizontal)?
So for example, do you mean the red-circled region in the left image have not reached a flat band condition? While instead the right image shows a good flat band condition? ( I need to mention here that the two PLDOS plots are not for identical devices, the left one has a device with short electrode, and the right one has longer one. My last question asking why 0.5V case and 0.0V case are not consistent is therefore nonsense..., I just made a mistake...)

 

Offline Petr Khomyakov

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The conduction and valence bands should be flat in the electrode extensions, and the band gap in the electrode extensions should be as in the corresponding electrodes. Please go through the following tutorial, https://docs.quantumwise.com/tutorials/atk_transport_calculations/atk_transport_calculations.html, to get an idea about the electrode extensions, screening length and other things related to transport calculations in QuantumATK.
« Last Edit: September 13, 2018, 20:38 by Petr Khomyakov »

Offline weixiang

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Thanks for your reply!