Thickness of metal gate and dielectric

[Amin]

Hello
I want to simulate the graphyne nanoribbon transistor based on this papers (https://doi.org/10.1016/j.orgel.2017.12.039 , https://doi.org/10.1039/C6RA27101D). My question involved in the value and method of the thickness of metal gate and dielectric.
On what basis were these parameters selected?
Is there any relationship between length and width of the central region with the width and the thickness of metal gate and dielectric?

[mlee]

If the material has large depletion(screening) region, it may require enough length.
https://docs.quantumatk.com/tutorials/inas_p-i-n_junction/inas_p-i-n_junction.html

If you have a defect in a bulk, it affects in the larger width. Therefore dielectric will be effected by defect.
But if it is pristine, these effect will be less.

[Amin]

Thank you for answering my question, but I did not understand how to accurately determine the appropriate thickness and dielectric constant. What is accurate thickness and dielectric of a graphyne nanoribbon with a length of 5 and a width of 2 nm? Is there a special formula for it or by simulating a specific output in ATK and checking the results, the thickness and dielectric can be found?

[mlee]

It is hard to say the accuracy of thickness and dielectric. Because it really depends on the materials and method (basis set, k-point sampling, etc). There is no formula. But you can test some thickness such as references using the ElectrostatcDifferencePotential analysis tool to check the convergence correctly. If there is structural periodicity in the electrodes of the A and/or B directions, we recommend to use the minimal because it can be speed up and reduce the memory usage.