conductance with/without gate structure

[J.g_johnson]

Hi,
   A graphene junction device with gate structure was built as the tutorial showed in: http://quantumwise.com/documents/tutorials/latest/GrapheneDevice/index.html/chap.buildingdevice.html#vnl.buildingdevice.gate
   
   The gate parameters were set as the tutorial, except that the metallic voltage was 0V this time. So the conductance of graphene junction device was calculated at 0V gate voltage and 0V bias voltage. The value is about 1.32E-6 S.

   In order to know whether the gate region has any effect on the transmission properties, a graphene junction device withou gate region was built by deleting the dielectric and metallic region in my previous work. So the conductance of graphene junction device was calculate at  0V bias voltage with gate region. This time the conductance value is about 1.22E-6 S.

  So here I am wondering if the gate region with might affect the device`s transmission peoperties (here I call it gate region effect), and how serious this influence. Is there any way to calculate the transmission properties, like conductance under certain gate voltage but without gate region effect.
 

[Anders Blom]

Why would you want to do that? What experimental situation would it correspond to? To have a gate in the system which actually isn't there physically...?

[J.g_johnson]

      I am planing to calculated the conductance under various gate voltage. The system is Al-molecule-Al two probe device. So first I have to know how to add the gate voltage on the system. This tutotial-A graphene junction device-shows adding a gate voltage by building a physically gate region.
      But the conductance would be also varied with gate region`s other parameters like thickness or area, which is not I expected. Gate voltage should be the only influence factor in my plan. This idea is motivated by the following theorical research on gate voltage effect.
      http://journals.aps.org/prb/abstract/10.1103/PhysRevB.73.045411
      I don`t know if the gate voltage can be added without using a physical gate region like the tutorial showed in ATK.  If no, how to decide the gate region`s physical parameters like thickness and position.