double gate tranistor

[ramkrishna]

Dear Sir,
       How can I make a double gate transistor ( source , drain, top gate and bottom gate) for 10 nm channel length silicon nanowire ?

Thanking you,
Ramkrishna Ghosh

[kstokbro]

Try the tutorial http://www.quantumwise.com/documents/tutorials/latest/GrapheneDevice/index.html/

In this tutorial you have a single electrostatic gate, however, you can define as many electrostatic gates as you want. Thus, you can easily extend this tutorial to a double gate transistor

[ramkrishna]

Dear Sir,
         I have few query about gate terminal,
 
(1)   In the tutorial, I have seen that there is a gap between left electrode cell and the gate terminal (as well as a gap between gate and right electrode cell). Now, for realistic transistor, there should be a little connection between the source (and drain) to the dielectric of the gate terminal. So, in this case, is it taken care of? If so, then what will be the minimum length for this gap? Is the gate length equal to the central region? If the gaps will be there, then how will we define this central region? 

(2)   In the tutorial, I also have seen that there is a gap between graphene and dielectric region, Is it necessary to keep a gap between these two or can we touch the dielectric with the graphene? If this gap is essential then what should be the minimum gap between the dielectric and graphene? If I want to use other material, then, will we keep same length for these gaps or how will these gaps vary?

Waiting for your earliest reply.

Regards
Ramkrishna
 
 

[kstokbro]

In a real device the gate constitutes of atoms and there is a disctance between the gate atoms and the central device.

The gap between the dielectric region and the central configuration mimicks this gap. The distance is between the position of the electrostatic image plane of the gate and the device. Usually the image plan is located a little outside a surface ~1 Å, thus in the tuturial it is assumed that the graphene is placed 2.4 Å above the SiO2 gate, which gives a distance of 1.4Å to the image plane.
However, the exact distance is not critical, and any value in the range 1-2 Å will give rather similar results.

For practical reasons the gate cannot be part of the equivalent electrode part of the central region, i.e. a distance from the edges of an electrode length. This is the reason for this gap. In a real device the gate will also not cover the electrode. Since the gate is purely electro-static, there is no current between gate and source/drain.

[ramkrishna]

Dear Sir,
        Thank you for your kind reply. I just want to know one more thing. In device calculation, if I want to calculate for ~10nm channel length then which method should I use so that I can get precise result? I am using 11.8.2 version of ATK. 

Regards
Ramkrishna