Author Topic: some questions about Gate Voltage  (Read 3456 times)

0 Members and 1 Guest are viewing this topic.

Offline Roc

  • QuantumATK Guru
  • ****
  • Posts: 104
  • Reputation: 0
    • View Profile
some questions about Gate Voltage
« on: February 24, 2009, 08:50 »
Dear everyone,

If we calculate the properties when the gate voltage is used, which atoms will often be applied gate voltage, just the molecule or the central scattering? Are there any special parameters to be set when applying the gate voltage?

Another, It seems diffult for the convergence when the bias voltage between two electrodes is more than +-2V. what about the situation on the gate voltage? In some experments, the gate voltage could be more than 30V, colud the ATK stimulate the situation? Does anyone have the experience, and could you give any advice?

Thanks!
« Last Edit: February 24, 2009, 08:56 by anyipeng »

Offline Nordland

  • QuantumATK Staff
  • Supreme QuantumATK Wizard
  • *****
  • Posts: 812
  • Reputation: 18
    • View Profile
Re: some questions about Gate Voltage
« Reply #1 on: February 24, 2009, 09:37 »
In the manual on the Gated TwoProbe, it states that you have to specify
the number of surface atoms, and in the manual it writes the following:
Quote
surface_atoms
    The number of surface atoms at each end of the central region. By surface atoms we here refer to the atoms that are not affected by the gate voltage. Should be given as a tuple, e.g. (5,10). In this specific case, the first 5 atoms and the 10 last atoms in the scattering_region_elements list, are not affected by the gate voltage.

I have not spent a long time playing around with the gate voltage, but I know that is less tricky to converge with gate voltage than usual bias. However I have found out, that if you apply high gate voltages, you need the best basis set or else you are on very rocking ground.

A small tip for getting normal bias calculation to go to a higher voltage before trouble arises, is to increase the length of the central region, hence for a Au-DBT-Au system, you must have more surface layers for 3 V than at 1V.
« Last Edit: February 24, 2009, 09:39 by Nordland »

Offline Anders Blom

  • QuantumATK Staff
  • Supreme QuantumATK Wizard
  • *****
  • Posts: 5411
  • Country: dk
  • Reputation: 89
    • View Profile
    • QuantumATK at Synopsys
Re: some questions about Gate Voltage
« Reply #2 on: February 24, 2009, 10:39 »
About the surface regions: this is a valuable tip, and quite obvious since the penetration of the electric field towards the electrodes much be screened by the surface layers, and this effect increases with the bias.