Dear Expert,
I would like to ask for your guidance on gate voltage settings in device simulations:
1. In single-gate devices, symmetric materials show nearly identical current whether the gate is on top or bottom. However, Janus materials show large differences depending on gate position. What causes this asymmetry?
2. For dual-gate devices with symmetric top and bottom gates, how are gate voltages set in the IV Characteristics module? When sweeping from 0 V to 1 V over 11 points, does 1 V mean both gates are biased at 1 V? If so, won’t the opposing electric fields cancel each other, reducing net field strength and weakening channel control?
Your insights would be greatly appreciated.
