Author Topic: How to design the gate electrode  (Read 3096 times)

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Offline John

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How to design the gate electrode
« on: January 11, 2012, 14:42 »
Dear Sir,
   Can you give any suggestions about the gate electrode, e.g., in the graphene device tutorial, how to decide the thickness of metallic and dielectric region and the distance between the graphene and dielectric region?
« Last Edit: January 11, 2012, 14:52 by John »

Offline Anders Blom

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Re: How to design the gate electrode
« Reply #1 on: January 15, 2012, 22:39 »
The metals don't need to be thick at all, since the electric potential is constant inside them. A few Angstrom is probably enough for the dielectrica.

In terms of distance, you should keep the gates as far away as possible (i.e. at the edge of the cell) so your real constraint is how large you can make the cell. The cell size costs quite a bit in memory when it grows large, esp. if it's large in more than one dimension. But a few nm is probably enough for the gate effect to be reasonably realistic.

Offline John

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Re: How to design the gate electrode
« Reply #2 on: January 16, 2012, 02:50 »
Thank you, Anders Blom.

Offline esp

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Re: How to design the gate electrode
« Reply #3 on: February 11, 2012, 00:18 »
I had things running nicely last week at about 20 minutes per transmission energy, then i must have changed something and now it is 1 hour per point ... i am suspecting it is because i had my dielectric and gate overhang the actual channel region perpendicular to the transport direction (z) ... i changed it back now and am waiting to see, but could that have been the problem?  would that make it run for roughly 3x the time ?

Offline Anders Blom

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Re: How to design the gate electrode
« Reply #4 on: February 11, 2012, 00:24 »
Since these are self-consistent loops, there are two factors controlling the simulation time: the time per step and the number of steps. If the number of steps is larger, that easily explains the total time difference - more steps means harder to converge, which can be caused by lots of factors (simply more difficult geometry, more charge transfer, higher bias = more non-linearity in the loop, etc). If the number of steps are similar, and you have longer time / step, then it's either the machine being slower (other processes? more MPI processes per node), or your changes introduced a switch of method - if you have default parameters ATK can sometimes detect a difference that causes it to switch internal methods. Although, in your case I doubt that's the reason, and my money is on more steps, which is easy enough to verify from the log file.