Author Topic: The STD configuration at 0K  (Read 258 times)

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Offline weixiang

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The STD configuration at 0K
« on: September 27, 2018, 21:27 »
Dear ATK experts,
I Have generated a Special Thermal Displacement (STD) configuration for a GNR geometry at 0K. From the common sense of physics, I know that there is no phonon at the absolute zero temperature.  So the STD configuration which use atomic displacement to account for the lattice phonon effect should be a perfect geometry at 0K, i.e. no phonon to account for at 0K. However, it is not as what I expected a perfect configuration of GNR. Instead, I can find some small out-of-plane displacement of the atoms.  The top image shows a perfect geometry of a GNR device and the bottom image shows an STD configuration of the same device at 0K. You can easily notice the difference.
 

So why there are still some atomic displacements even at 0K? Is my understanding of phonon mode wrong here that there does exist some phonon mode at 0K? Or Possibly that I calculate the STD configuration wrongly?

Any help is appreciated!

Offline Petr Khomyakov

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Re: The STD configuration at 0K
« Reply #1 on: September 28, 2018, 09:27 »
I Have generated a Special Thermal Displacement (STD) configuration for a GNR geometry at 0K. From the common sense of physics, I know that there is no phonon at the absolute zero temperature.  So the STD configuration which use atomic displacement to account for the lattice phonon effect should be a perfect geometry at 0K, i.e. no phonon to account for at 0K.

The common sense of classical physics would suggest that there is no atom motion at 0 K. However, quantum physics suggests something different, and that is called zero point motion of atoms, https://en.wikipedia.org/wiki/Zero-point_energy.  I would suggest reading some textbook on quantum mechanics.

As a matter of fact, the special thermal displacement method allows one to account for this purely quantum-mechanical effect, and this is a strength of this method, compared to some other methods such MD-Landauer method described at https://docs.quantumwise.com/casestudies/md_landauer/md_landauer.html.  The two methods should agree in the limit of high temperature.

Offline weixiang

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Re: The STD configuration at 0K
« Reply #2 on: September 29, 2018, 08:37 »
Thank you very much for the help! ;D

Offline weixiang

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Re: The STD configuration at 0K
« Reply #3 on: September 29, 2018, 18:21 »
In addition, I found my results contradictory with the result shown in Fig.1c) of the paper Phys. Rev. B 96, 161404(R) when I apply the STD method in my calculation for GNR TFET device I-V curves at different temperatures (0K, 300K, and 600K). The Fig.1) below shows that as the temperature increase, both the On and Off state current will increase, this is very reasonable and is consistent with a lot of experimental and simulational results for different materials (Si, InAs, MoS2, graphene etc. ) based MOSFET and TFET. It seems like a universal law that temperature increase will lead to the current increase in a FET.

However, the calculated temperature of my GNR TFET device shows the opposite-- as the temperature increases, the current decreases as shown in the image below (gate voltage is 0V, which is at nearly On state) . I have gone over my scripts many times and I think I have applied the STD method in the right way. But I can still not able to found the reason for such a weird and unreasonable result. I have attached my scripts for your reference.

Thanks! Please help!




Offline Petr Khomyakov

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Re: The STD configuration at 0K
« Reply #4 on: October 1, 2018, 09:35 »
- There is not much to say, looking at your scripts, at least I see no STD generation related parts - so no information how you did it. Moreover, do you have a solid proof that the current should always increase with the temperature? I would guess that that might be system dependent.  For example, your system is quasi-1D, not 2D or 3D - would it make a difference? Also, in conventional 3D intrinsic semiconductors, the current increases with the temperature, but metals or highly degenerate semiconductors behave in a completely opposite manner.

- Did you try checking the behavior for other V_gate?

- In the original paper you have cited the current goes slightly down in some temperature range. I guess this range does not need to be universal, i.e., it can be system system dependent.

- There are many more computational settings in relation to self-consistent calculation and current computing, you may try testing. For example, are you sure that 201 points for 4 eV interval is enough for accurate calculation of the current?